The present invention relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with elevated source and drain regions.
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. An ultra-large scale integrated circuit can include over 1 million transistors.
The ULSI circuit can include CMOS field effect transistors (FETS) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking capability of the silicon dioxide spacers.
As the size of transistors disposed on ICs decreases, transistors with shallow and ultra-shallow source/drain extensions become more difficult to manufacture. For example, a small transistor may require ultra-shallow source and drain extensions with less than 30 nanometer (nm) junction depth. Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically downward into the bulk semiconductor substrate. Also, conventional ion implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate.
The source region and drain regions can be raised by selective silicon (Si) epitaxy to make connections to source and drain contacts less difficult. The raised source and drain regions provide additional material for contact silicidation processes and reduce deep source/drain junction resistance and source/drain series resistance. However, the epitaxy process that forms the raised source and drain regions generally requires high temperatures exceeding 1000xc2x0 C. (e.g., 1100-1200xc2x0 C.). These high temperatures increase the thermal budget of the process and can adversely affect the formation of steep retrograde well regions and ultra shallow source/drain extensions.
The high temperatures, often referred to as high thermal budget, can produce significant thermal diffusion which can cause shorts between the source and drain region (between the source/drain extensions). The potential for shorting between the source and drain region increases as gate lengths decrease.
Thus, there is a need for an integrated circuit or electronic device that includes transistors not susceptible to shorts caused by dopant thermal diffusion. Further still, there is a need for transistors with elevated source and drain regions manufactured in an optimized annealing process. Even further still, there is a need for elevated source and drain regions which are formed in a low thermal budget (low temperature) process.
An exemplary embodiment relates to a method of manufacturing and integrated circuit. The integrated circuit includes a gate structure on a substrate. The substrate includes a shallow source and drain extension dopant implant. The gate structure includes a gate conductor. The method includes providing an amorphous semiconductor material above the substrate and over the gate structure, removing a portion of the amorphous semiconductor material to expose the gate conductor, doping the amorphous semiconductor material at a source location and a drain location to form a deep source region and a deep drain region, and forming a single crystalline semiconductor material from the amorphous semiconductor material via solid phase epitaxy.
Another exemplary embodiment relates to a method of manufacturing an ultralarge scale integrated circuit including a transistor. The method includes steps of providing a gate structure on a top surface of a substrate, depositing an amorphous semiconductor material, polishing the amorphous semiconductor material, doping the amorphous semiconductor material, and crystallizing the amorphous semiconductor material. The amorphous semiconductor material is deposited above the top surface of the substrate. The amorphous semiconductor material is doped for a deep source region and a deep drain region of the transistor. The amorphous semiconductor material is crystallized via solid phase epitaxy.
Yet another embodiment relates to a process of forming a transistor with elevated source and drain regions. The process includes providing a gate structure having a gate conductor above a substrate, providing a shallow source drain extension dopant implant to the substrate, providing a spacer structure to the gate conductor, and depositing amorphous semiconductor material above the substrate and the gate structure. The method also includes steps of providing a deep source drain dopant implant to the amorphous semiconductor material and crystallizing the amorphous semiconductor material to form single crystalline material via solid phase epitaxy.